Z8F1680SH020SG Datasheet, PDF (186/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
161
• Noise Filter Control (NFCTL[2:0]) input selects the width of the up/down saturating
counter digital filter; the available width ranges from 4 to 11 bits
• The digital filter output features hysteresis
• Provides an active low Saturated State output (FiltSatB) which is used as an indication
of the presence of noise
12.2.1. Architecture
Figure 25 displays how the noise filter is integrated with the LIN-UART on a LIN
network.
Figure 25. Noise Filter System Block Diagram
12.2.2. Operation
Figure 26 displays the operation of the noise filter both with and without noise. The noise
filter in this example is a 2-bit up/down counter which saturates at 00b and 11b. A 2-bit
counter is shown for convenience, the operation of wider counters is similar. The output of
the filter switches from 1 to 0, when the counter counts down from 01b to 00b; and
switches from 0 to 1, when the counter counts up from 10b to 11b. The noise filter delays
the receive data by three System Clock cycles.
The FiltSatB signal is checked when the filtered RxD is sampled in the center of the bit
time. The presence of noise (FiltSatB = 1 at center of bit time) does not mean that the
sampled data is incorrect, but just that the filter is not in its ‘saturated’ state of all 1s or all
0s. If FiltSatB = 1 then RxD is sampled during a receive character, the NE bit in the
PS025015-1212
PRELIMINARY
LIN-UART