Z8F1680SH020SG Datasheet, PDF (130/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
105
Table 54 provides an example initialization sequence for configuring Timer 0 in DEMOD-
ULATION Mode and initiating operation.
Table 54. DEMODULATION Mode Initialization Example
Register
Value Comment
T0CTL0
T0CTL1
T0CTL2
C0H
04H
11H
TMODE[3:0] = 1100B selects DEMODULATION Mode.
TICONFIG[1:0] = 10B enables interrupt only on Capture events.
CSC = 0 selects the Timer Input from the GPIO pin.
PWMD[2:0] = 000B has no effect.
INPCAP = 0 has no effect.
TEN = 0 disables the timer.
PRES[2:0] = 000B sets prescaler to divide by 1.
TPOLHI,TPOL = 10 enables trigger and Capture on both rising and falling
edges of Timer Input.
TCLKS = 1 enables 32 kHz peripheral clock as timer clock source
T0H
00H
Timer starting value = 0001H.
T0L
01H
T0RH
ABH
Timer reload value = ABCDH
T0RL
CDH
T0PWM0H 00H
Initial PWM0 value = 0000H
T0PWM0L 00H
T0PWM1H 00H
Initial PWM1 value = 0000H
T0PWM1H 00H
T0NFC
C0H
NFEN = 1 enables noise filter
NFCTL = 100B enables 8-bit up/down counter
PAADDR
02H
Selects Port A Alternate Function control register.
PACTL[1:0] 11B
PACTL[0] enables Timer 0 Input alternate function.
PACTL[1] enables Timer 0 Output alternate function.
IRQ0ENH[5] 0B
Disables the Timer 0 interrupt.
IRQ0ENL[5] 0B
T0CTL1
84H
TEN = 1 enables the timer. All other bits remain in their appropriate settings.
Notes:
Notes: After receiving the input trigger (rising or falling edge), Timer 0 will:
1. Start counting on the timer clock.
2. Upon receiving a Timer 0 Input rising edge, save the Capture value in the T0PWM0 registers, generate an inter-
rupt, and continue to count.
3. Upon receiving a Timer 0 Input falling edge, save the Capture value in the T0PWM1 registers, generate an inter-
rupt, and continue to count.
4. After the timer count to ABCD clocks, set the reload event flag and reset the Timer count to the start value.
PS025015-1212
PRELIMINARY
Timers