Z8F1680SH020SG Datasheet, PDF (238/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
213
SPI BRG Interrupt Interval (s) = System Clock Period (s)  BRG[15:0]
16.4. ESPI Control Register Definitions
This section defines the features of the following ESPI Control registers.
ESPI Data Register: see page 213
ESPI Transmit Data Command and Receive Data Buffer Control Register: see page 214
ESPI Control Register: see page 215
ESPI Mode Register: see page 217
ESPI Status Register: see page 219
ESPI State Register: see page 220
ESPI Baud Rate High and Low Byte Registers: see page 221
16.4.1. ESPI Data Register
The ESPI Data Register, shown in Table 109, addresses both the outgoing Transmit Data
Register and the incoming Receive Data Register. Reads from the ESPI Data Register
return the contents of the Receive Data Register. The Receive Data Register is updated
with the contents of the Shift Register at the end of each transfer. Writes to the ESPI Data
Register load the Transmit Data Register unless TDRE = 0. Data is shifted out starting
with bit 7. The last bit received resides in bit position 0.
With the ESPI configured as a Master, writing a data byte to this register initiates the data
transmission. With the ESPI configured as a Slave, writing a data byte to this register
loads the Shift Register in preparation for the next data transfer with the external Master.
In either the MASTER or SLAVE modes, if TDRE = 0, writes to this register are ignored.
When the character length is less than 8 bits (as set by the NUMBITS field in the ESPI
Mode Register), the transmit character must be left justified in the ESPI Data Register. A
received character of less than 8 bits is right justified (last bit received is in bit position 0).
For example, if the ESPI is configured for 4-bit characters, the transmit characters must be
written to ESPIDATA[7:4] and the received characters are read from ESPIDATA[3:0].
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface