Z8F1680SH020SG Datasheet, PDF (270/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
245
17.3.2. I²C Interrupt Status Register
The read-only I²C Interrupt Status Register, shown in Table 120, indicates the cause of any
current I²C interrupt and provides status of the I²C controller. When an interrupt occurs,
one or more of the TDRE, RDRF, SAM, ARBLST, SPRS or NCKI bits is set. The GCA
and RD bits do not generate an interrupt but rather provide status associated with the SAM
bit interrupt.
Table 120. I²C Interrupt Status Register (I2CISTAT = F51H)
Bits
Field
Reset
R/W
Address
7
TDRE
1
R
6
RDRF
0
R
5
SAM
0
R
4
3
GCA
RD
0
0
R
R
F51H
2
ARBLST
0
R
1
SPRS
0
R
0
NCKI
0
R
Bit
[7]
TDRE
[6]
RDRF
[5]
SAM
[4]
GCA
[3]
RD
Description
Transmit Data Register Empty
When the I²C controller is enabled, this bit is 1 when the I²C Data Register is empty. When set,
this bit causes the I²C controller to generate an interrupt, except when the I²C controller is
shifting in data during the reception of a byte or when shifting an address and the RD bit is set.
This bit clears by writing to the I2CDATA Register.
Receive Data Register Full
This bit is set = 1 when the I²C controller is enabled and the I²C controller has received a byte
of data. When asserted, this bit causes the I²C controller to generate an interrupt. This bit
clears by reading the I2CDATA Register.
Slave Address Match
This bit is set = 1 if the I²C controller is enabled in SLAVE Mode and an address is received
that matches the unique slave address or General Call Address (if enabled by the GCE bit in
the I²C Mode Register). In 10-bit addressing mode, this bit is not set until a match is achieved
on both address bytes. When this bit is set, the RD and GCA bits are also valid. This bit clears
by reading the I2CISTAT Register.
General Call Address
This bit is set in SLAVE Mode when the General Call Address or Start byte is recognized (in
either 7 or 10 bit SLAVE Mode). The GCE bit in the I²C Mode Register must be set to enable
recognition of the General Call Address and Start byte. This bit clears when IEN = 0 and is
updated following the first address byte of each SLAVE Mode transaction. A General Call
Address is distinguished from a Start byte by the value of the RD bit (RD = 0 for General Call
Address, 1 for Start byte).
Read
This bit indicates the direction of transfer of the data. It is set when the Master is reading data
from the Slave. This bit matches the least-significant bit of the address byte after the start
condition occurs (for both MASTER and SLAVE modes). This bit clears when IEN = 0 and is
updated following the first address byte of each transaction.
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller