Z8F1680SH020SG Datasheet, PDF (342/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
317
secutive. It is possible to write to or read from other registers within the unlocking/locking
operation.
When selecting a new clock source, the primary oscillator failure detection circuitry and
the Watchdog Timer oscillator failure circuitry must be disabled. If POFEN and WOFEN
are not disabled prior to a clock switch-over, it is possible to generate an interrupt for a
failure of either oscillator. The Failure detection circuitry can be enabled anytime after a
successful write of SCKSEL in the Oscillator Control Register.
The internal precision oscillator is enabled by default. If the user code changes to a differ-
ent oscillator, it may be appropriate to disable the IPO for power savings. Disabling the
IPO does not occur automatically.
24.1.2. Clock Failure Detection and Recovery
Clock failure detection and recovery are provided for the primary oscillator. Clock failure
detection is provided for the Watchdog Timer oscillator.
24.1.2.1. Primary Oscillator Failure
The Z8 Encore! XP F1680 Series devices can generate nonmaskable interrupt-like events
when the primary oscillator fails. To maintain system function in this situation, the clock
failure recovery circuitry automatically forces the Watchdog Timer oscillator to drive the
system clock. The Watchdog Timer oscillator must be enabled to allow the recovery.
Although this oscillator runs at a much slower speed than the original system clock, the
CPU continues to operate allowing execution of a clock failure vector and software rou-
tines that either remedy the oscillator failure or issue a failure alert. This automatic switch-
over is not available, if the Watchdog Timer is the primary oscillator. It is also unavailable
if the Watchdog Timer oscillator is disabled, though it is not necessary to enable the
Watchdog Timer reset function outlined in the Watchdog Timer chapter on page 140.
The primary oscillator failure detection circuitry asserts if the system clock frequency
drops below 1 kHz ±50%. If an external signal is selected as the system oscillator, it is pos-
sible that a very slow but nonfailing clock can generate a failure condition. Under these
conditions, do not enable the primary oscillator failure circuitry (i.e., clear the POFEN
bit).
24.1.2.2. Watchdog Timer Failure
In the event of a Watchdog Timer oscillator failure, a similar nonmaskable interrupt-like
event is issued. This event does not trigger an attendant clock switch-over, but alerts the
CPU of the failure. After a Watchdog Timer failure, it is no longer possible to detect a pri-
mary oscillator failure. The failure detection circuitry does not function if the Watchdog
Timer is used as the primary oscillator or if the Watchdog Timer oscillator has been dis-
abled. For either of these cases, it is necessary to disable the detection circuitry by clearing
the WDFEN bit of the OSCCTL0 Register.
PS025015-1212
PRELIMINARY
Oscillator Control