Z8F1680SH020SG Datasheet, PDF (166/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
141
WDT Reload
Value
(Hex)
0400
FFFF
Table 80. Watchdog Timer Approximate Time-Out Delays
WDT Reload
Value (Decimal)
1024
65,536
Approximate Time-Out Delay
(with 10 kHz Typical WDT Oscillator Frequency)
Typical Description
102 ms Reset default value time-out delay.
6.55 s Maximum time-out delay.
11.1.1. Watchdog Timer Refresh
When first enabled, the WDT is loaded with the value in the WDT Reload registers. The
WDT then counts down to 0000H unless a WDT instruction is executed by the eZ8 CPU.
Execution of the WDT instruction causes the downcounter to be reloaded with the WDT
reload value stored in the WDT Reload registers. Counting resumes following the reload
operation.
When the eZ8 CPU is operating in DEBUG Mode (through the OCD), the WDT is contin-
uously refreshed to prevent unnecessary WDT time-outs.
11.1.2. Watchdog Timer Time-Out Response
The WDT times out when the counter reaches 0000H. A time-out of the WDT generates
either a system exception or a Reset. The WDT_RES option bit determines the time-out
response of the WDT. For information about programming the WDT_RES option bit, see
the Flash Option Bits section on page 276.
11.1.2.1. WDT System Exception in Normal Operation
If it is configured to generate a system exception when a time-out occurs, the WDT issues
an exception request to the interrupt controller. The eZ8 CPU responds to the request by
fetching the System Exception vector and executing code from the vector address. After
time-out and system exception generation, the WDT is reloaded automatically and contin-
ues counting.
11.1.2.2. WDT System Exception in STOP Mode
The WDT automatically initiates a Stop Mode Recovery and generates a system exception
request if configured to generate a system exception when a time-out occurs and the CPU
is in STOP Mode. Both the WDT status bit and the stop bit in the Reset Status Register are
set to 1 following a WDT time-out in STOP Mode.
Upon completion of the Stop Mode Recovery, the eZ8 CPU responds to the system excep-
tion request by fetching the System Exception vector and executing code from the vector
address.
PS025015-1212
PRELIMINARY
Watchdog Timer