Z8F1680SH020SG Datasheet, PDF (250/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
225
Table 118. I²C Master/Slave Controller Registers (Continued)
Name
I²C Baud Rate High
I²C Baud Rate Low
I²C State
I²C Mode
I²C Slave Address
Abbreviation
I2CBRH
I2CBRL
I2CSTATE
I2CMODE
I2CSLVAD
Description
High byte of baud rate generator initialization value.
Low byte of baud rate generator initialization value.
State register.
Selects MASTER or SLAVE modes, 7-bit or 10-bit addressing;
configure address recognition, define slave address bits [9:8].
Defines slave address bits [7:0].
17.2. Operation
The I²C Master/Slave Controller operates in MASTER/SLAVE Mode, SLAVE ONLY
Mode, or with master arbitration. In MASTER/SLAVE Mode, it can be used as the only
Master on the bus or as one of the several masters on the bus, with arbitration. In a Multi-
Master environment, the controller switches from MASTER to SLAVE Mode on losing
arbitration.
Though slave operation is fully supported in MASTER/SLAVE Mode, if a device is
intended to operate only as a slave, then SLAVE ONLY mode can be selected. In SLAVE
ONLY mode, the device will not initiate a transaction, even if the software inadvertently
sets the start bit.
17.2.1. SDA and SCL Signals
The I²C circuit sends all addresses, Data and Acknowledge signals over the SDA line,
with most-significant bit first. SCL is the clock for the I²C bus. When the SDA and SCL
pin alternate functions are selected for their respective GPIO ports, the pins are automati-
cally configured for open-drain operation.
The Master is responsible for driving the SCL clock signal. During the Low period of the
clock, a slave can hold the SCL signal Low to suspend the transaction if it is not ready to
proceed. The Master releases the clock at the end of the Low period and notices that the
clock remains Low instead of returning to a High level. When the slave releases the clock,
the I²C master continues the transaction. All data is transferred in bytes; there is no limit to
the amount of data transferred in one operation. When transmitting address, data, or an
Acknowledge, the SDA signal changes in the middle of the Low period of SCL. When
receiving address, Data, or an Acknowledge; the SDA signal is sampled in the middle of
the High period of SCL.
A low-pass digital filter can be applied to the SDA and SCL receive signals by setting the
Filter Enable (FILTEN) bit in the I²C Control Register. When the filter is enabled, any
glitch that is less than a system clock period in width will be rejected. This filter should be
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller