Z8F1680SH020SG Datasheet, PDF (318/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
293
Modes section on page 42) and configured for a threshold voltage of 2.4 V or greater (see
the Trim Bit Address Space section on page 282).
A System Reset that occurs during a write operation (such as a pin reset or watchdog timer
reset) also perturbs the byte currently being written. All other bytes in the array remain
unperturbed.
22.2.4. Optimizing NVDS Memory Usage for Execution
Speed
As listed in Table 161, the NVDS read time varies drastically, this discrepancy being a
trade-off for minimizing the frequency of writes that require post-write page erases. The
NVDS read time of address N is a function of the number of writes to addresses other than
N since the most recent write to address N, as well as the number of writes since the most
recent page erase. Neglecting effects caused by page erases and results caused by the ini-
tial condition in which the NVDS is blank, a rule of thumb is that every write since the
most recent page erase causes read times of unwritten addresses to increase by 0.8 µs up to
a maximum of 258 µs.
Table 161. NVDS Read Time
Operation
Read
Write
Illegal Read
Illegal Write
Minimum
Latency (µs)
71
126
6
7
Maximum
Latency (µs)
258
136
6
7
If NVDS read performance is critical to your software architecture, you can optimize your
code for speed by using either of the methods listed below.
• Periodically refresh all addresses that are used; the most useful method. The optimal
use of NVDS, in terms of speed, is to rotate the writes evenly among all planned ad-
dresses, bringing all reads closer to the minimum read time. Because the minimum read
time is much less than the write time, however, actual speed benefits are not always re-
alized.
• Use as few unique addresses as possible to optimize the impact of refreshing.
PS025015-1212
PRELIMINARY
Nonvolatile Data Storage