Z8F1680SH020SG Datasheet, PDF (327/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
302
enabled, the OCD ignores the BRK signal and the BRK instruction operates as an NOP
instruction.
If breakpoints are enabled, the OCD can be configured to automatically enter DEBUG
mode, or to loop on the break instruction. If the OCD is configured to loop on the BRK
instruction, then the CPU remains able to service interrupt requests.
The loop on a BRK instruction can service interrupts in the background. For interrupts to
be serviced in the background, there cannot be any breakpoints in the interrupt service
routine. Otherwise, the CPU stops on the breakpoint in the interrupt routine. For interrupts
to be serviced in the background, interrupts must also be enabled. Interrupts are typically
disabled during critical sections of code where interrupts do not occur (such as adjusting
the stack pointer or modifying shared data).
Through the OCD, host debugger software can poll the IDLE bit of the OCDSTAT Regis-
ter to determine if the OCD is looping on a BRK instruction. When the host must stop the
CPU on the BRK instruction on which it is looping, the host must not set the DBGMODE
bit of the OCDCTL register. The CPU may have vectored to an interrupt service routine.
Instead, the host clears the BRKLOOP bit, thereby allowing the CPU to finish the inter-
rupt service routine and return to the BRK instruction. When the CPU returns to the BRK
instruction on which it was previously looping, it automatically sets the DBGMODE bit
and enters DEBUG mode.
The majority of the OCD commands remain disabled when the eZ8 CPU is looping on a
BRK instruction. The eZ8 CPU must be in DEBUG mode before these commands can be
issued.
23.2.8.1. Breakpoints in Flash Memory
The BRK instruction is op code 00H, which corresponds to the fully programmed state of
a byte in Flash memory. To implement a breakpoint, write 00H to the appropriate address,
overwriting the current instruction. To remove a breakpoint, erase the corresponding page
of Flash memory and reprogram with the original data.
23.2.9. OCDCNTR Register
The On-Chip Debugger contains a multipurpose 16-bit Counter Register. It can be used
for the following:
• Count system clock cycles between breakpoints
• Generate a BRK when it counts down to 0
• Generate a BRK when its value matches the Program Counter
When configured as a counter, the OCDCNTR Register starts counting when the On-Chip
Debugger exits DEBUG mode and stops counting when it enters DEBUG mode again or
PS025015-1212
PRELIMINARY
On-Chip Debugger