Z8F1680SH020SG Datasheet, PDF (132/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
107
Timer
Clock
Timer
TxIN
NEF
NFEN, NFCTL
Noise Filter
TxOUT
TxIN
TxOUT
Figure 12. Noise Filter System Block Diagram
9.2.7.1. Operation
Figure 13 displays the operation of the Noise Filter with and without noise. The Noise
Filter in this example is a 2-bit up/down counter which saturates at 00 and 11. A 2-bit
counter is described for convenience; the operation of wider counters is similar. The
output of the filter switches from 1 to 0 when the counter counts down from 01 to 00 and
switches from 0 to 1 when the counter counts up from 10 to 11. The Noise Filter delays
the receive data by three timer clock cycles.
The NEF output signal is checked when the filtered TxIN input signal is sampled. The Timer
samples the filtered TxIN input near the center of the bit time. The NEF signal must be
sampled at the same time to detect whether there is noise near the center of the bit time. The
presence of noise (NEF = 1 at the center of the bit time) does not mean that the sampled data
is incorrect; rather, it is intended to be an indicator of the level of noise in the network.
PS025015-1212
PRELIMINARY
Timers