Z8F1680SH020SG Datasheet, PDF (191/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
166
Bit
[2]
TDRE
[1]
TXE
[0]
CTS
Description (Continued)
Transmitter Data Register Empty
This bit indicates that the Transmit Data Register is empty and ready for additional data.
Writing to the Transmit Data Register resets this bit.
0 = Do not write to the Transmit Data Register.
1 = The Transmit Data Register is ready to receive an additional byte for transmission.
Transmitter Empty
This bit indicates that the Transmit Shift Register is empty and character transmission is
finished.
0 = Data is currently transmitting.
1 = Transmission is complete.
Clear to Send Signal
When this bit is read it returns the level of the CTS signal. If LBEN = 1, the CTS input signal is
replaced by the internal Receive Data Available signal to provide flow control in loopback
mode. CTS only affects transmission if the CTSE bit = 1.
Table 86. LIN-UART Status 0 Register—LIN Mode (U0STAT0 = F41H)
Bit
7
6
5
Field
RDA
PLE
OE
Reset
0
0
0
R/W
R
R
R
Address
Note: R = Read.
4
3
2
1
0
FE
BRKD TDRE
TXE
ATB
0
0
1
1
0
R
R
R
R
R
F41H, F49H
Bit
[7]
RDA
[6]
PLE
Description
Receive Data Available
This bit indicates that the Receive Data Register has received data. Reading the Receive Data
Register clears this bit.
0 = The Receive Data Register is empty.
1 = There is a byte in the Receive Data Register.
Physical Layer Error
This bit indicates that transmit and receive data do not match when a LIN slave or master is
transmitting. This could be by a fault in the physical layer or multiple devices driving the bus
simultaneously. Reading the Status 0 Register or the Receive Data Register clears this bit.
0 = Transmit and Receive data match.
1 = Transmit and Receive data do not match.
PS025015-1212
PRELIMINARY
LIN-UART