Z8F1680SH020SG Datasheet, PDF (233/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
208
To Slave’s SS Pin
From Slave
To Slave
ESPI Master
SS
MISO
MOSI
8-bit Shift Register
Bit 0
Bit 7
To Slave
SCK
Baud Rate
Generator
Figure 39. ESPI Configured as an SPI Master in a Single Master, Single Slave System
To Slave #2s SS Pin
To Slave #1s SS Pin
From Slaves
To Slaves
GPIO
GPIO
ESPI Master
MISO
MOSI
8-bit Shift Register
Bit 0
Bit 7
To Slaves
SCK
Baud Rate
Generator
Figure 40. ESPI Configured as an SPI Master in a Single Master, Multiple Slave System
16.3.4.2. Multi-Master SPI Operation
In a Multi-Master SPI system, all SCK pins are tied together, all MOSI pins are tied
together and all MISO pins are tied together. All SPI pins must be configured in open-
drain mode to prevent bus contention. At any time, only one SPI device is configured as
the Master and all other devices on the bus are configured as slaves. The Master asserts the
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface