Z8F1680SH020SG Datasheet, PDF (230/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
205
SCK (SSMD = 00,
PHASE = 0,
CLKPOL = 0,
SSPO = 0)
MOSI, MISO
Bit0 Bit7 Bit6
Bit1 Bit0
Bit7 Bit 6
Data Register
Tx n Rx n-1
empty
Tx n+1
Rx n
empty
Shift Register ^{Tx/Rx n-1}
TDRE
RDRNE
Tx/Rx n
Tx/Rx n+1
ESPI Interrupt
Figure 36. SPI Mode (SSMD = 00)
16.3.3.2. Synchronous Frame Sync Pulse Mode
This mode is selected by setting the SSMD field of the Mode Register to 10. This mode is
typically used for continuous transfer of fixed length frames where the frames are
delineated by a pulse of duration one SCK period. The SSV bit in the ESPI Transmit Data
Command register does not control the SS pin directly in this mode. SSV must be set
before or in sync with the first transmit data byte being written. The SS signal will assert 1
SCK cycle before the first data bit and will stop after 1 SCK period. SCK is active from
the initial assertion of SS until the transaction end due to lack of transmit data.
The transaction is terminated by the Master when it no longer has data to send. If TDRE=1
at the end of a character, the SS output will remain detached and SCK stops after the last
bit is transferred. The TUND bit (transmit underrun) will assert in this case. After the
transaction has completed, hardware will clear the SSV bit. Figure 37 displays a frame
with synchronous frame sync pulse mode.
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface