Z8F1680SH020SG Datasheet, PDF (241/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
216
Bit
Description (Continued)
[6,0]
ESPI Enable and Direction Control
ESPIEN1, 00 = The ESPI block is disabled. BRG can be used as a general-purpose timer by setting
ESPIEN0
BRGCTL = 1.
01 = Receive Only Mode. Use this setting in SLAVE Mode if software application is receiving
data but not sending. TDRE will not assert. Transmitted data will be all 1s. Not valid in
MASTER Mode since Master must source data to drive the transfer.
10 = Transmit Only Mode
Use this setting in MASTER or SLAVE Mode when the software application is sending
data but not receiving. RDRNE will not assert.
11 = Transmit/Receive Mode
Use this setting if the software application is both sending and receiving information. Both
TDRE and RDRNE will be active.
[5]
Baud Rate Generator Control
BRGCTL The function of this bit depends upon ESPIEN1,0. When ESPIEN1,0 = 00, this bit allows
enabling the BRG to provide periodic interrupts.
If the ESPI is disabled
0 = The Baud Rate Generator timer function is disabled. Reading the Baud Rate High and Low
registers returns the BRG reload value.
1 = The Baud Rate Generator timer function and time-out interrupt is enabled. Reading the
Baud Rate High and Low registers returns the BRG Counter value.
If the ESPI is enabled
0 = Reading the Baud Rate High and Low registers returns the BRG reload value. If MMEN =
1, the BRG is enabled to generate SCK. If MMEN = 0, the BRG is disabled.
1 = Reading the Baud Rate High and Low registers returns the BRG Counter value. If MMEN =
1, the BRG is enabled to generate SCK. If MMEN = 0 the BRG is enabled to provide a
Slave SCK time-out. See the SLAVE Mode Abort error description on page 211.
Caution: If reading the counter one byte at a time while the BRG is counting keep in mind that
the values will not be in sync. Zilog recommends reading the counter using (2-byte) word
reads.
[4]
PHASE
Phase Select
Sets the phase relationship of the data to the clock. For more information about operation of
the PHASE bit, see the ESPI Clock Phase and Polarity Control section on page 201.
[3]
Clock Polarity
CLKPOL 0 = SCK idles Low (0).
1 = SCK idles High (1).
[2]
WOR
Wire-OR (Open-Drain) Mode Enabled
0 = ESPI signal pins not configured for open-drain.
1 = All four ESPI signal pins (SCK, SS, MISO and MOSI) configured for open-drain function.
This setting is typically used for multi-Master and/or Multi-Slave
configurations.
[1]
MMEN
ESPI MASTER Mode Enable
This bit controls the data I/O pin selection and SCK direction.
0 = Data out on MISO, data in on MOSI (used in SPI SLAVE Mode), SCK is an input.
1 = Data out on MOSI, data in on MISO (used in SPI MASTER Mode), SCK is an output.
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface