Z8F1680SH020SG Datasheet, PDF (257/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
232
The first 7 bits transmitted in the first byte are 11110XX. The 2 XX bits are the two most
significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
Read/Write control bit (which is cleared to 0). The transmit operation is performed in the
same manner as 7-bit addressing.
Observe the following steps for a master transmit operation to a 10-bit addressed slave:
1. The software initializes the MODE field in the I²C Mode Register for MASTER/
SLAVE Mode with 7- or 10-bit addressing (the I²C bus protocol allows the mixing of
slave address types). The MODE field selects the address width for this mode when
addressed as a slave (but not for the remote slave). The software asserts the IEN bit in
the I²C Control Register.
2. The software asserts the TXI bit of the I²C Control Register to enable transmit inter-
rupts.
3. The I²C interrupt asserts because the I²C Data Register is empty.
4. The software responds to the TDRE interrupt by writing the first Slave Address byte
(11110xx0). The least-significant bit must be 0 for the write operation.
5. The software asserts the start bit of the I²C Control Register.
6. The I²C controller sends a start condition to the I²C Slave.
7. The I²C controller loads the I²C Shift Register with the contents of the I²C Data Reg-
ister.
8. After one bit of the address is shifted out by the SDA signal, the transmit interrupt
asserts.
9. The software responds by writing the second byte of address into the contents of the
I²C Data Register.
10. The I²C controller shifts the remainder of the first byte of the address and the Write bit
out via the SDA signal.
11. The I²C slave sends an Acknowledge by pulling the SDA signal Low during the next
High period of SCL. The I²C controller sets the ACK bit in the I²C Status Register.
If the slave does not acknowledge the first address byte, the I²C controller sets the
NCKI bit in the I²C Status Register, sets the ACKV bit and clears the ACK bit in the
I²C State Register. The software responds to the Not Acknowledge interrupt by setting
the stop bit and clearing the TXI bit. The I²C controller flushes the second address
byte from the Data Register, sends a stop condition on the bus and clears the stop and
NCKI bits. The transaction is complete and the following steps can be ignored.
12. The I²C controller loads the I²C Shift Register with the contents of the I²C Data
Register (2nd address byte).
13. The I²C controller shifts the second address byte out via the SDA signal. After the
first bit has been sent, the transmit interrupt asserts.
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller