Z8F1680SH020SG Datasheet, PDF (150/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
125
10.3.3. PWM Output Operation
In a PWM OUTPUT operation, the timer generates a PWM output signal on the channel
output pin (T4CHA, T4CHB, T4CHC, or T4CHD). The channel output toggles whenever
the timer count matches the channel compare value (defined in the MCTCHyH and
MCTCHyL registers). In addition, a channel interrupt is generated and the channel event
flag is set in the status register. The timer continues counting according to its programmed
mode.
The channel output signal begins with the output value = CHPOL and then transitions to
CHPOL when timer value matches the PWM value. If timer mode is Count Modulo, the
channel output signal returns to output = CHPOL when timer reaches the reload value and
is reset. If timer mode is Count up/down, channel output signal returns to output =
CHPOL when the timer count matches the PWM value again (when counting down).
10.3.4. Capture Operation
In a CAPTURE operation, the current timer count is recorded when the selected transition
occurs on T4CHA, T4CHB, T4CHC or T4CHD. The Capture count value is written to the
Channel High and Low Byte registers. In addition, a channel interrupt is generated and the
channel event flag (CHyEF) is set in the Channel Status Register. The CHPOL bit in the
Channel Control Register determines if the Capture occurs on a rising edge or a falling
edge of the Channel Input signal. The timer continues counting according to the pro-
grammed mode.
10.4. Multi-Channel Timer Interrupts
The Multi-Channel Timer provides a single interrupt which has five possible sources.
These sources are the internal timer and the four channel inputs (T4CHA, T4CHB,
T4CHC, T4CHD).
10.4.1. Timer Interrupt
If enabled by the TCIEN bit of the MCTCTL0 Register, the timer interrupt will be gener-
ated when the timer completes a count cycle. This occurs during transition from counter =
reload register value to counter = 0 in count modulo mode and occurs during transition
from counter = 1 to counter = 0 in count up/down mode.
10.4.2. Capture/Compare Channel Interrupt
A channel interrupt is generated whenever there is a successful Capture/Compare Event
on the Timer Channel and the associated CHIEN bit is set.
PS025015-1212
PRELIMINARY
Multi-Channel Timer