Z8F1680SH020SG Datasheet, PDF (263/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
238
S
Start
W
Write
A
Acknowledge
A
Not Acknowledge
P
Stop
17.2.6.5. Slave Receive Transaction with 7-Bit Address
The data transfer format for writing data from a Master to a Slave in 7-bit address mode is
displayed in Figure 47. The procedure that follows describes the I²C Master/Slave Con-
troller operating as a slave in 7-bit addressing mode and receiving data from the bus mas-
ter.
S Slave Address
W=0
A Data A Data A Data A/A P/S
Figure 47. Data Transfer Format—Slave Receive Transaction with 7-Bit Address
1. The software configures the controller for operation as a slave in 7-bit addressing
mode, as follows:
a. Initialize the MODE field in the I²C Mode Register for either SLAVE ONLY
mode or MASTER/SLAVE Mode with 7-bit addressing.
b. Optionally set the GCE bit.
c. Initialize the SLA[6:0] bits in the I²C Slave Address Register.
d. Set IEN = 1 in the I²C Control Register. Set NAK = 0 in the I²C Control Register.
2. The bus master initiates a transfer, sending the address byte. In SLAVE Mode, the I²C
controller recognizes its own address and detects that R/W bit = 0 (written from the
master to the slave). The I²C controller acknowledges indicating it is available to
accept the transaction. The SAM bit in the I2CISTAT Register is set to 1, causing an
interrupt. The RD bit in the I2CISTAT Register is cleared to 0, indicating a Write to
the slave. The I²C controller holds the SCL signal Low waiting for the software to
load the first data byte.
3. The software responds to the interrupt by reading the I2CISTAT Register (which
clears the SAM bit). After seeing the SAM bit to 1, the software checks the RD bit.
Because RD = 0, no immediate action is required until the first byte of data is
received. If software is only able to accept a single byte, it sets the NAK bit in the
I2CCTL Register at this time.
4. The Master detects the Acknowledge and sends the byte of data.
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller