Z8F1680SH020SG Datasheet, PDF (242/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
217
Bits
Field
Reset
R/W
Address
Bit
[7:5]
SSMD
16.4.4. ESPI Mode Register
The ESPI Mode Register, shown in Table 112, configures the character bit width and
mode of the ESPI I/O pins.
Table 112. ESPI Mode Register (ESPIMODE)
7
6
5
SSMD
000
R/W
4
3
2
NUMBITS[2:0]
0
0
0
R/W
R/W
R/W
F63H
1
SSIO
0
R/W
0
SSPO
0
R/W
Description
Slave Select Mode
This field selects the behavior of SS as a framing signal. For a detailed description of
these modes, see Slave Select on page 200.
000 = SPI Mode
When SSIO = 1, the SS pin is driven directly from the SSV bit in the Transmit Data
Command Register. The Master software should set SSV (or a GPIO output if the SS pin
is not connected to the appropriate Slave) to the asserted state prior to or on the same
clock cycle that the Transmit Data Register is written with the initial byte. At the end of a
frame (after the last RDRNE event), SSV will be automatically deasserted by hardware.
In this mode, SCK is active only for data transfer (one clock cycle per bit transferred).
001 = Loopback Mode
When ESPI is configured as Master (MMEN = 1), the outputs are deasserted and data is
looped from Shift Register Out to Shift Register In. When ESPI is configured as a Slave
(MMEN = 0) and SS in asserts, MISO (Slave output) is tied to MOSI (Slave input) to
provide an asynchronous remote loop back (echo) function.
010 = I2S Mode (Synchronous Framing with SSV)
In this mode, the value from SSV will be output by the Master on the SS pin with one SCK
period before the data and will remain in that state until the start of the next frame.
Typically this mode is used to send back to back frames with SS alternating on each
frame. A frame boundary is indicated in the Master when SSV changes. A frame
boundary is detected in the Slave by SS changing state. The SS framing signal will lead
the frame by one SCK period. In this mode SCK will run continuously, starting with the
initial SS assertion. Frames will run back-to-back as long as software continues to
provide data. An example of this mode is the I²S protocol (Inter IC Sound) which is used
to carry left and right channel audio data with the SS signal indicating which channel is
being sent. In SLAVE Mode, the change in state of SS (Low to High or High to Low)
triggers the start of a transaction on the next SCK cycle.
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface