Z8F1680SH020SG Datasheet, PDF (160/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
135
10.7.7. Multi-Channel Timer Channel Status 0 and Status 1
Registers
The Multi-Channel Timer Channel Status 0 and Status 1 registers (MCTCHS0,
MCTCHS1) indicate channel overruns and channel capture/compare events.
Table 76. Multi-Channel Timer Channel Status 0 Register (MCTCHS0)
Bit
7
6
5
4
3
2
Field
Reserved
CHDEO CHCEO
Reset
0
0
0
0
0
0
R/W
R
R
R
R
R
R
Address
See note.
Note: If a 01H is in the Subaddress Register, it is accessible through Subregister 0.
1
CHBEO
0
R
0
CHAEO
0
R
Bit
[7:4]
[3:0]
CHyEO
Description
Reserved; must be 0.
Channel y Event Flag Overrun
This bit indicates that an overrun error has occurred. An overrun occurs when a new Capture/
Compare event occurs before the previous CHyEF bit is cleared. Clearing the associated
CHyEF bit in the MCTCHS1 register clears this bit. This bit is cleared when TEN=0 (TEN is the
MSB of MCTCTL1).
0 = No Overrun.
1 = Capture/Compare Event Flag Overrun
PS025015-1212
PRELIMINARY
Multi-Channel Timer