Z8F1680SH020SG Datasheet, PDF (235/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
210
From Master
To Master
From Master
SPI Slave
SS
MISO
MOSI
8-bit Shift Register
Bit 7
Bit 0
From Master
SCK
Figure 41. ESPI Configured as an SPI Slave
16.3.5. Error Detection
Error events detected by the ESPI block are described in this section. Error events gener-
ate an ESPI interrupt and set a bit in the ESPI Status Register. The error bits of the ESPI
Status Register are Read/Write 1 to clear.
16.3.5.1. Transmit Underrun
A transmit underrun error occurs for a Master with SSMD = 10 or 11 when a character
transfer completes and TDRE = 1. In these modes when a transmit underrun occurs the
transfer will be aborted (SCK will halt and SSV will be deasserted). For a Master in SPI
mode (SSMD = 00), a transmit underrun is not signaled since SCK will pause and wait for
the Data Register to be written.
In SLAVE Mode, a transmit underrun error occurs if TDRE = 1 at the start of a transfer.
When a transmit underrun occurs in SLAVE Mode, ESPI will transmit a character of all
1s.
A transmit underrun sets the TUND bit in the ESPI Status Register to 1. Writing a 1 to
TUND clears this error flag.
16.3.5.2. Mode Fault (Multi-Master Collision)
A mode fault indicates when more than one Master is trying to communicate simultane-
ously (a Multi-Master collision) in SPI mode. The mode fault is detected when the enabled
Master’s SS input pin is asserted. For this to happen the Control and Mode registers must
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface