Z8F1680SH020SG Datasheet, PDF (94/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
69
Table 36. Trap and Interrupt Vectors in Order of Priority
Program Memory
Priority* Vector Address Interrupt or Trap Source
Highest 0002H
Reset (not an interrupt)
0004H
Watchdog Timer (see the Watchdog Timer chapter on page 140)
003AH
Primary Oscillator Fail Trap (not an interrupt)
003CH
Watchdog Timer Oscillator Fail Trap (not an interrupt)
0006H
Illegal Instruction Trap (not an interrupt)
0008H
Timer 2
000AH
Timer 1
000CH
Timer 0
000EH
UART 0 receiver
0010H
0012H
UART 0 transmitter
I²C
0014H
SPI
0016H
ADC
0018H
Port A7, selectable rising or falling input edge or LVD (see the Reset,
Stop Mode Recovery and Low-Voltage Detection chapter on page 31)
001AH
Port A6, selectable rising or falling input edge or Comparator 0 Output
001CH
Port A5, selectable rising or falling input edge or Comparator 1 Output
001EH
Port A4 or Port D4, selectable rising or falling input edge
0020H
Port A3 or Port D3, selectable rising or falling input edge
0022H
Port A2 or Port D2, selectable rising or falling input edge
0024H
Port A1 or Port D1, selectable rising or falling input edge
0026H
Port A0, selectable rising or falling input edge
0028H
Reserved
002AH
Multi-channel Timer
002CH
UART 1 receiver
002EH
UART 1 transmitter
0030H
Port C3, both input edges
0032H
Port C2, both input edges
0034H
Port C1, both input edges
Lowest 0036H
Port C0, both input edges
0038H
Reserved
Note: *The order of priority is only meaningful when considering identical interrupt levels. This priority varies depend-
ing on different interrupt level settings. See the Interrupt Vectors and Priority section on page 71 for details.
PS025015-1212
PRELIMINARY
Interrupt Controller