Z8F1680SH020SG Datasheet, PDF (362/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
337
Table 186. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic
AND dst, src
Symbolic Operation
dst ← dst AND src
Address
Mode
dst src
r
r
r
Ir
R
R
R IR
R IM
ANDX dst, src dst ← dst AND src
IR IM
ER ER
ER IM
ATM
Block all interrupt and
DMA requests during
execution of the next
3 instructions
BCLR bit, dst dst[bit] ← 0
r
BIT p, bit, dst dst[bit] ← p
r
BRK
Debugger Break
BSET bit, dst dst[bit] ← 1
r
BSWAP dst dst[7:0] ← dst[0:7]
R
BTJ p, bit, src, if src[bit] = p
r
dst
PC ← PC + X
Ir
BTJNZ bit, src, if src[bit] = 1
r
dst
PC ← PC + X
Ir
BTJZ bit, src,
dst
CALL dst
CCF
if src[bit] = 0
PC ← PC + X
SP ← SP -2
@SP ← PC
PC ← dst
C ← ~C
r
Ir
IRR
DA
Flags notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
Op
Code(s)
(Hex)
52
53
54
55
56
57
58
59
2F
Flags
Fetch Instr.
C Z S V D H Cycles Cycles
–* *0–– 2
3
2
4
3
3
3
4
3
3
3
4
–* *0–– 4
3
4
3
–––––– 1
2
E2
–* *0–– 2
2
E2
–* *0–– 2
2
00
–––––– 1
1
E2
–* *0–– 2
2
D5 X * * 0 – – 2
2
F6
–––––– 3
3
F7
3
4
F6
–––––– 3
3
F7
3
4
F6
–––––– 3
3
F7
3
4
D4
–––––– 2
6
D6
3
3
EF
* – – – – –- 1
2
PS025015-1212
PRELIMINARY
eZ8 CPU Instruction Set