Z8F1680SH020SG Datasheet, PDF (62/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
37
5.2.4. External Reset Input
The RESET pin has a Schmitt-triggered input and an internal pull-up resistor. When the
RESET pin is asserted for a minimum of four system clock cycles, the device progresses
through the System Reset sequence. Because of the possible asynchronicity of the system
clock and reset signals, the required reset duration can be as short as three clock periods
and as long as four. A reset pulse three clock cycles in duration might trigger a Reset; a
pulse four cycles in duration always triggers a Reset.
While the RESET input pin is asserted Low, the F1680 Series MCU remains in the Reset
state. If the RESET pin is held Low beyond the System Reset time-out, the device exits the
Reset state on the system clock rising edge following RESET pin deassertion. Following a
System Reset initiated by the external RESET pin, the EXT status bit in the RSTSTAT
Register is set to 1.
5.2.5. External Reset Indicator
During System Reset or when enabled by the GPIO logic (see the Port A–E Control Reg-
isters section on page 60), the RESET pin functions as an open-drain (active Low) reset
mode indicator in addition to the input functionality. This Reset output feature allows the
F1680 Series MCU to reset other components to which it is connected, even if that reset is
caused by internal sources such as POR, VBO, or WDT events.
After an internal Reset event occurs, the internal circuitry begins driving the RESET pin
Low. The RESET pin is held Low by the internal circuitry until the appropriate delay
listed in Table 9 on page 32 has elapsed.
5.2.6. On-Chip Debugger Initiated Reset
A POR can be initiated using the OCD by setting the RST bit in the OCD Control Regis-
ter. The OCD block is not reset, but the rest of the chip goes through a normal System
Reset. The RST bit automatically clears during the system reset. Following the System
Reset the POR bit in the WDT Control Register is set.
5.3.
Stop Mode Recovery
STOP Mode is entered by execution of a stop instruction by the eZ8 CPU. For detailed
STOP Mode information, see the Low-Power Modes section on page 42. During Stop
Mode Recovery, the CPU is held in reset for 4 IPO cycles.
Stop Mode Recovery does not affect On-chip registers other than the Reset Status
(RSTSTAT) register and the Oscillator Control Register (OSCCTL). After any Stop Mode
Recovery, the IPO is enabled and selected as the system clock. If another system clock
source is required or IPO disabling is required, the Stop Mode Recovery code must
PS025015-1212
P R E L I M I N A R Y Reset, Stop Mode Recovery and Low-Voltage