Z8F1680SH020SG Datasheet, PDF (239/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
214
Table 109. ESPI Data Register (ESPIDATA)
Bits
7
6
5
4
3
2
1
0
Field
DATA
Reset
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F60H
Bit
[7:0]
DATA
Description
Data
Transmit and/or receive data. Writes to the ESPIDATA register load the Shift Register. Reads
from the ESPIDATA register return the value of the Receive Data Register.
16.4.2. ESPI Transmit Data Command and Receive Data
Buffer Control Register
The ESPI Transmit Data Command and Receive Data Buffer Control Register, shown in
Table 110, provides control of the SS pin when it is configured as an output (MASTER
Mode), clear receive data buffer function and flag. The CRDR, TEOF and SSV bits can be
controlled by a bus write to this register.
Table 110. ESPI Transmit Data Command and Receive Data Buffer Control Register (ESPITDCR)
Bits
Field
Reset
R/W
Address
7
CRDR
0
R/W
6
5
RDFLAG
00
R
4
3
2
Reserved
0
0
0
R
R
R
F61H
1
TEOF
0
R/W
0
SSV
0
R/W
Bit
Description
[7]
Clear Receive Data Register
CRDR Writing 1 to this bit is used to clear all data in receive data buffer.
[6:5]
Receive Data Buffer Flag
RDFLAG This bit is used to indicate how many bytes stored in receive buffer.
00 = 0 or 4 bytes (see RDRNE in the ESPI Status Register).
01 = 1 byte.
02 = 2 bytes.
03 = 3 bytes.
[4:2]
Reserved
These bits are reserved and must be programmed to 000.
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface