Z8F1680SH020SG Datasheet, PDF (224/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
199
16.2. ESPI Signals
The four ESPI signals are:
• Master-In/Slave-Out (MISO)
• Master-Out/Slave-In (MOSI)
• Serial Clock (SCK)
• Slave Select (SS)
The following paragraphs discuss these signals as they operate in both MASTER and
SLAVE modes.
16.2.1. Master-In/Slave-Out
The Master-In/Slave-Out (MISO) pin is configured as an input in a Master device and as
an output in a slave device. Data is transferred most significant bit first. The MISO pin of
a Slave device is placed in a high-impedance state if the Slave is not selected. When the
ESPI is not enabled, this signal is in a high-impedance state. The direction of this pin is
controlled by the MMEN bit of the ESPI Control Register.
16.2.2. Master-Out/Slave-In
The Master-Out/Slave-In (MOSI) pin is configured as an output in a Master device and as
an input in a slave device. Data is transferred most significant bit first. When the ESPI is
not enabled, this signal is in a high-impedance state. The direction of this pin is controlled
by the MMEN bit of the ESPI Control Register.
16.2.3. Serial Clock
The Serial Clock (SCK) synchronizes data movement both in and out of the Shift Register
via the MOSI and MISO pins. In MASTER Mode (MMEN = 1), the ESPI’s Baud Rate
Generator creates the serial clock and drives it out on its SCK pin to the slave devices. In
SLAVE Mode, the SCK pin is an input. Slave devices ignore the SCK signal, unless their
SS pin is asserted.
The Master and Slave are each capable of exchanging a character of data during a
sequence of NUMBITS clock cycles (see Table 112 on page 217). In both Master and
Slave ESPI devices, data is shifted on one edge of the SCK and is sampled on the opposite
edge where data is stable. SCK phase and polarity is determined by the PHASE and
CLKPOL bits in the ESPI Control Register.
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface