Z8F1680SH020SG Datasheet, PDF (246/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
221
Table 115 defines the valid ESPI states.
Table 115. ESPISTATE Values
ESPISTATE Value
00_0000
00_0001
01_0001
10_1110
10_1111
10_1100
10_1101
10_1010
10_1011
10_1000
10_1001
10_0110
10_0111
10_0100
10_0101
10_0010
10_0011
10_0000
10_0001
Description
Idle
Slave Wait For SCK
Master Ready
Bit 7 Receive
Bit 7 Transmit
Bit 6 Receive
Bit 6 Transmit
Bit 5 Receive
Bit 5 Transmit
Bit 4 Receive
Bit 4 Transmit
Bit 3 Receive
Bit 3 Transmit
Bit 2 Receive
Bit 2 Transmit
Bit 1 Receive
Bit 1 Transmit
Bit 0 Receive
Bit 0 Transmit
16.4.7. ESPI Baud Rate High and Low Byte Registers
The ESPI Baud Rate High and Low Byte registers, shown in Tables 116 and 117, combine
to form a 16-bit reload value, BRG[15:0], for the ESPI Baud Rate Generator. The ESPI
baud rate is calculated using the following equation:
SPI
Baud Rate bits § s
=
S----y----s--t--e---m-------C----l--o---c---k-----F----r--e---q----u---e---n---c---y-----_{---H----z----}
2  BRG[15:0]
The minimum baud rate is obtained by setting BRG[15:0] to 0000H for a clock divisor
value of (2 x 65536 = 131072).
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface