Z8F1680SH020SG Datasheet, PDF (256/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
231
11. The I²C slave sends an Acknowledge (by pulling the SDA signal Low) during the next
High period of SCL. The I²C controller sets the ACK bit in the I²C Status Register.
If the slave does not acknowledge the address byte, the I²C controller sets the NCKI
bit in the I²C Status Register, sets the ACKV bit and clears the ACK bit in the I²C
State Register. The software responds to the Not Acknowledge interrupt by setting the
stop bit and clearing the TXI bit. The I²C controller flushes the Transmit Data Regis-
ter, sends a stop condition on the bus and clears the stop and NCKI bits. The transac-
tion is complete and the following steps can be ignored.
12. The I²C controller loads the contents of the I²C Shift Register with the contents of the
I²C Data Register.
13. The I²C controller shifts the data out via the SDA signal. After the first bit is sent, the
transmit interrupt asserts.
14. If more bytes remain to be sent, return to Step 9.
15. When there is no more data to be sent, the software responds by setting the stop bit of
the I²C Control Register (or the start bit to initiate a new transaction).
16. If no additional transaction is queued by the master, the software can clear the TXI bit
of the I²C Control Register.
17. The I²C controller completes transmission of the data on the SDA signal.
18. The I²C controller sends a stop condition to the I²C bus.
Note: If the slave terminates the transaction early by responding with a Not Acknowledge during
the transfer, the I²C controller asserts the NCKI interrupt and halts. The software must ter-
minate the transaction by setting either the stop bit (end transaction) or the start bit (end
this transaction, start a new one). In this case, it is not necessary for software to set the
FLUSH bit of the I2CCTL Register to flush the data that was previously written but not
transmitted. The I²C controller hardware automatically flushes transmit data in the not
acknowledge case.
17.2.5.5. Master Write Transaction with a 10-Bit Address
Figure 44 displays the data transfer format from a Master to a 10-bit addressed slave.
S
Slave Address
1st Byte
W=0
A
Slave Address
2nd Byte
A
Data
A
Data
A/A F/S
Figure 44. Data Transfer Format—Master Write Transaction with a 10-Bit Address
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller