Z8F1680SH020SG Datasheet, PDF (336/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
311
Bit
[3]
BRKPC
[2]
BRKZRO
[1]
[0]
RST
Description
Break when PC == OCDCNTR
If this bit is set to 1, then the OCDCNTR Register is used as a hardware breakpoint. When
the program counter matches the value in the OCDCNTR Register, DBGMODE is
automatically set to 1. If this bit is set, the OCDCNTR Register does not count when the
CPU is running.
0 = OCDCNTR is set up as a counter.
1 = OCDCNTR generates a hardware break when PC == OCDCNTR.
Break when OCDCNTR == 0000H
If this bit is set, then the OCD automatically sets the DBGMODE bit when the OCDCNTR
Register counts down to 0000H. If this bit is set, the OCDCNTR Register is not reset when
the part exits DEBUG Mode.
0 = OCD does not generate BRK when OCDCNTR decrements to 0000H.
1 = OCD sets DBGMODE to 1 when OCDCNTR decrements to 0000H.
Reserved; must be 0.
Reset
Setting this bit to 1 resets the device. The controller goes through a normal POR sequence
with the exception that the On-Chip Debugger is not reset. This bit is automatically cleared
to 0 when the reset finishes.
0 = No effect.
1 = Reset the device.
PS025015-1212
PRELIMINARY
On-Chip Debugger