Z8F1680SH020SG Datasheet, PDF (175/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
150
The LIN-UART is now configured for interrupt-driven data reception. When the LIN-
UART Receiver interrupt is detected, the associated ISR performs the following:
1. Checks the LIN-UART Status 0 Register to determine the source of the interrupt-error,
break, or received data.
2. If the interrupt is due to data available, read the data from the LIN-UART Receive
Data Register. If operating in MULTIPROCESSOR (9-bit) Mode, further actions may
be required depending on the MULTIPROCESSOR Mode bits MPMD[1:0].
3. Execute the IRET instruction to return from the ISR and await more data.
12.1.6. Clear To Send Operation
The Clear To Send (CTS) pin, if enabled by the CTSE bit of the LIN-UART Control 0
Register performs flow control on the outgoing transmit data stream. The Clear To Send
(CTS) input pin is sampled one system clock before any new character transmission
begins. To delay transmission of the next data character, an external receiver must reduce
CTS at least one system clock cycle before a new data transmission begins. For multiple
character transmissions, this operation is typically performed during the stop bit
transmission. If CTS stops in the middle of a character transmission, the current character
is sent completely.
12.1.7. External Driver Enable
The LIN-UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This
feature reduces the software overhead associated using a GPIO pin to control the trans-
ceiver when communicating on a multitransceiver bus, such as RS-485.
Driver Enable is a programmable polarity signal which envelopes the entire transmitted
data frame including parity and stop bits as illustrated in Figure 22. The Driver Enable
signal asserts when a byte is written to the LIN-UART Transmit Data Register. The Driver
Enable signal asserts at least one bit period and no greater than two bit periods before the
start bit is transmitted. This allows a set-up time to enable the transceiver. The Driver
Enable signal deasserts one system clock period after the last stop bit is transmitted. This
system clock delay allows both time for data to clear the transceiver before disabling it, as
well as the ability to determine if another character follows the current character. In the
event of back-to-back characters (new data must be written to the Transmit Data Register
before the previous character is completely transmitted) the DE signal is not deasserted
between characters. The DEPOL bit in the LIN-UART Control Register 1 sets the polarity
of the Driver Enable signal.
PS025015-1212
PRELIMINARY
LIN-UART