Z8F1680SH020SG Datasheet, PDF (237/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
212
A receive interrupt is generated by the RDRNE status bit when the ESPI block is enabled,
the DIRQE bit is set and a character transfer completes. At the end of the character
transfer, the contents of the Shift Register are transferred into the Data Register, causing
the RDRNE bit to assert. The RDRNE bit is cleared when the Data Buffer is read as
empty. If information is being transmitted but not received by the software application, the
receive interrupt can be eliminated by selecting Transmit Only mode (ESPIEN1,0 = 10) in
either MASTER or SLAVE modes. When information is being sent and received under
interrupt control, RDRNE and TDRE will both assert simultaneously at the end of a
character transfer. Since the new receive data is in the Data Register, the receive interrupt
must be serviced before the transmit interrupt.
ESPI error interrupts occur if any of the TUND, COL, ABT and ROVR bits in the ESPI
Status Register are set. These bits are cleared by writing a 1. If the ESPI is disabled
(ESPIEN1, 0 = 00), an ESPI interrupt can be generated by a Baud Rate Generator time-
out. This timer function must be enabled by setting the BRGCTL bit in the ESPICTL
register. This timer interrupt does not set any of the bits of the ESPI Status Register.
16.3.7. ESPI Baud Rate Generator
In ESPI MASTER Mode, the Baud Rate Generator creates a lower frequency serial clock
(SCK) for data transmission synchronization between the Master and the external Slave.
The input to the Baud Rate Generator is the system clock. The ESPI Baud Rate High and
Low Byte registers combine to form a 16-bit reload value, BRG[15:0], for the ESPI Baud
Rate Generator. The ESPI baud rate is calculated using the following equation:
SPI Baud Rate bits § s = ^S-----^y---^s---^t---^e---^m-------^C-₂----^l-_-^o----^c-_B--^k--_R----^F-_G---^r--_[-^e-₁--^q-₅---^u:--₀-^e---_]-ⁿ---^c----^y-----^---^H-----^z----^
Minimum baud rate is obtained by setting BRG[15:0] to 0000H for a clock divisor value
of (2 x 65536 = 131072).
When the ESPI is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with interrupt on time-out. Observe the following steps to configure the Baud Rate Gener-
ator as a timer with interrupt on time-out:
1. Disable the ESPI by clearing the ESPIEN1,0 bits in the ESPI Control Register.
2. Load the appropriate 16-bit count value into the ESPI Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BRGCTL bit in the ESPI Control Register to 1.
When configured as a general purpose timer, the SPI BRG interrupt interval is calculated
using the following equation:
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface