SH7020 Datasheet, PDF (98/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

BAMRL: Break address mask register L.
Bit: 15
14
13
12
11
10
Bit name: BAM15 BAM14 BAM13 BAM12 BAM11 BAM10
Initial value: 0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W
9
BAM9
0
R/W
8
BAM8
0
R/W
Bit:
Bit name:
Initial value:
R/W:
7
BAM7
0
R/W
6
BAM6
0
R/W
5
BAM5
0
R/W
4
BAM4
0
R/W
3
BAM3
0
R/W
2
BAM2
0
R/W
1
BAM1
0
R/W
0
BAM0
0
R/W
• BAMRL bits 15–0 (break address mask 15–0 (BAM15–BAM0)): BAM15–BAM0 specify
whether bits BA15–BA0 of the break address set in BARH are masked or not.
Bits 15–0: BAMn
0
1
n = 31–0
Description
Break address bit BAn is included in the break condition (initial value)
Break address bit BAn is not included in the break condition
6.2.3 Break Bus Cycle Register (BBR)
The break bus cycle register (BBR) is a 16-bit read/write register that selects the following four
break conditions:
• CPU cycle or DMA cycle
• Instruction fetch or data access
• Read or write
• Operand size (byte, word, long word).
A reset initializes BBR to H'0000. It is not initialized in the standby mode.
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