SH7020 Datasheet, PDF (96/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 6.1 User Break Controller Registers
Name
Abbr.
R/W Address*
Initial
Value Bus width
Break address register high
BARH R/W H'5FFFF90 H'0000 8, 16, 32
Break address register low
BARL R/W H'5FFFF92 H'0000 8, 16, 32
Break address mask register high
BAMRH R/W H'5FFFF94 H'0000 8, 16, 32
Break address mask register low
BAMRL R/W H'5FFFF96 H'0000 8, 16, 32
Break bus cycle register
BBR
R/W H'5FFFF98 H'0000 8, 16, 32
Note: Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For details
on the register addresses, see section 8.3.5, Description of Areas.
6.2 Register Descriptions
6.2.1 Break Address Registers (BAR)
There are two break address registers—break address register H (BARH) and break address
register L (BARL)—that together form a single group. Both are 16-bit read/write registers. BARH
stores the upper bits (bits 31–16) of the address of the break condition. BARL stores the lower bits
(bits 15–0) of the address of the break condition. A reset initializes both BARH and BARL to
H'0000. Neither is initialized in standby mode.
BARH: Break address register H.
Bit:
Bit name:
Initial value:
R/W:
15
BA31
0
R/W
14
BA30
0
R/W
13
BA29
0
R/W
12
BA28
0
R/W
11
BA27
0
R/W
10
BA26
0
R/W
9
BA25
0
R/W
8
BA24
0
R/W
Bit:
Bit name:
Initial value:
R/W:
7
BA23
0
R/W
6
BA22
0
R/W
5
BA21
0
R/W
4
BA20
0
R/W
3
BA19
0
R/W
2
BA18
0
R/W
1
BA17
0
R/W
0
BA16
0
R/W
• BARH Bits 15–0 (break address 31–16 (BA31–BA16)): BA31–BA16 store the upper bit
values (bits 31–16) of the address of the break condition.
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