SH7020 Datasheet, PDF (124/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

• Bit 12 (burst operation enable (BE)): BE selects whether or not to perform burst operation, a
high speed page mode. When burst operation is not selected (0), the row address is not
compared but instead is transferred to the DRAM every time and full access is performed.
When burst operation is selected (1), row addresses are compared and burst operation with the
same row address as the previous is performed (in this access, no row address is output and the
column address and CAS signal alone are output).
Bit 12: BE
0
1
Description
Normal mode: full access (initial value)
Burst operation: high-speed page mode
• Bit 11 (CAS duty (CDTY)): CDTY selects 35% or 50% of the T_C state as the high-level duty
ratio of the signal CAS in the short-pitch access. When cleared to 0, the CAS signal high level
duty is 50%; when set to 1, it is 35%. Only set to 1 when the operating frequency is a
minimum of 10 MHz.
Bit 11: CDTY
0
1
Description
CAS signal high level duty cycle is 50% of the T_C state (initial value)
CAS signal high level duty cycle is 35% of the T_C state
• Bit 10 (multiplex enable bit (MXE)): MXE determines whether or not DRAM row and column
addresses are multiplexed. When cleared to 0, addresses are not multiplexed; when set to 1,
they are multiplexed.
Bit 10: MXE
0
1
Description
Multiplex of row and column addresses disabled (initial value)
Multiplex of row and column addresses enabled
• Bits 9 and 8 (multiplex shift count 1 and 0 (MXC1 and MXC0)): Shift row addresses
downward by a certain number of bits (8–10) when row and column addresses are multiplexed
(MXE = 1). Regardless of the MXE bit setting, these bits also select the range of row addresses
compared in burst operation.
106 RENESAS