SH7020 Datasheet, PDF (492/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

CK
A21–A0
RAS
CAS
Silent
T_p
T_r
T_c
cycle
T_c
t_AD
t_AD
Row address Column address
t_RASD1
t_ASC
Column address
t_RASD2
RD (Write)
WRH, WRL,
WR (Write)
t_WSD3
t_WSD4
AD15–AD0
DPH, DPL
(Write)
t_WDD2
t_WDH
t_WPDD2
t_WPDH
DPH, DPL
(Write)
DACK0
DACK1
(Write)
t_{DACD4 tDACD5}
t_DACD5
Figure 19.25 (b) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Write)
Note: For details of the silent cycle, see section 8.5.5, Burst Operation.
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