SH7020 Datasheet, PDF (218/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

T1 Tw T2
T1 Tw T2
CK
DREQ
Bus cycle
CPU CPU CPU
DMAC
CPU
DMAC
CPU
DACK
Note: When DREQ is negated at the third state of the DMAC cycle, the next DMA transfer will
be executed because the sampling is done at the second state of the DMAC cycle.
Figure 9.17 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level
detection and DACK active low) (Single address mode, bus cycle = 2 states + 1 wait state)
T1 Tw T2 T1 Tw T2
CK
DREQ
Bus cycle
CPU CPU CPU DMAC (R) DMAC (W) CPU CPU
DACK
DMAC (R): DMAC read cycle
DMAC (W): DMAC write cycle
Figure 9.18 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level
detection and DACK active low) (Dual address mode, bus cycle = 2 states + 1 wait state)
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