SH7020 Datasheet, PDF (336/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

11.3.4 TPC Output Non-Overlap Operation
Setting Procedures for TPC Output Non-Overlap Operation (figure 11.6):
1. Select GRA and GRB as output compare registers (output disable) with the timer I/O control
register (TIOR).
2. Set the TPC output trigger cycle to GRB and the non-overlap cycle to GRA.
3. Select the counter clock with the TPSC2–TPSC0 bits of the timer control register (TCR).
Select the counter clear sources with the CCLR1 and CCLR0 bits.
4. Set the timer interrupt enable register (TIER) to enable IMIA interrupts. Transfers to the NDR
can also be set using the DMAC.
5. Set the initial output value in the I/O port data register to be used by TPC.
6. Set the I/O port control register to be used by TPC as the TP pin function (11).
7. Set to 1 the bit that performs TPC output to the next data enable register (NDER).
8. Select the ITU compare match that will be the TPC output trigger using the TPC output control
register (TPCR).
9. Select the group that performs the non-overlap operation in the TPC output mode register
(TPMR).
10. Set the next TPC output value in the NDR.
11. Set 1 in the STR bit of the timer start register (TSTR) and start the timer counter counting.
12. Set the next output value in the NDR whenever an IMIA interrupt is generated.
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