SH7020 Datasheet, PDF (209/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Address Modes:
• Single Address Mode
In the single address mode, both the transfer source and destination are external; one
(selectable) is accessed by a DACK signal while the other is accessed by an address. In this
mode, the DMAC performs the DMA transfer in 1 bus cycle by simultaneously outputting a
transfer request acknowledge DACK signal to one external device to access it while outputting
an address to the other end of the transfer. Figure 9.6 shows an example of a transfer between
an external memory and an external device with DACK in which the external device outputs
data to the data bus while that data is written in external memory in the same bus cycle.
External address bus External data bus
SH microcomputer
DMAC
External
memory
Read Write
**
(1) (2)
External device
with DACK
DACK
DREQ
: Data flow
Note:
The read/write direction is decided by the RS3-RS0 bits of the CHCRn registers. If RS3-
RS0=0010, the direction is shown as case 1 (circled number above); if RS3-RS0=0010,
the direction is shown as case 2. Also, DACK output (when writing) indicates case 2.
Figure 9.6 Data Flow in Single Address Mode
Two types of transfers are possible in the single address mode: 1) transfers between external
devices with DACK and memory-mapped external devices, and 2) transfers between external
devices with DACK and external memory. The only transfer requests for either of these is the
external request (DREQ). Figure 9.7 shows the DMA transfer timing for the single address
mode.
192 RENESAS