SH7020 Datasheet, PDF (23/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 1.1 Features of the SH7020 and SH7021 Microcomputers
Feature
CPU
Operating modes
Description
Original Hitachi architecture
32-bit internal data paths
General-register machine:
• Sixteen 32-bit general registers
• Three 32-bit control registers
• Four 32-bit system registers
RISC-type instruction set:
• Instruction length: 16-bit fixed length for improved code
efficiency
• Load-store architecture (basic arithmetic and logic operations
are executed between registers)
• Delayed unconditional branch instructions reduce pipeline
disruption
• Instruction set optimized for C language
Instruction execution time: one instruction/cycle (50 ns/instruction
at 20-MHz operation)
Address space: 4 Gbytes available on the architecture
On-chip multiplier: multiplication operations (16 bits × 16 bits →
32 bits) executed in 1–3 cycles, and multiplication/accumulation
operations (16 bits × 16 bits + 42 bits → 42 bits) executed in 2–3
cycles
Five-stage pipeline
Operating modes:
• On-chip ROMless mode
• On-chip ROM mode
Processing states:
• Power-on reset state
• Manual reset state
• Exception processing state
• Program execution state
• Power-down state
• Bus-released state
Power-down states:
• Sleep mode
• Software standby mode
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