SH7020 Datasheet, PDF (148/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 8.8 Number of States and Number of Wait States in the Access Cycles to External
Memory Spaces
Area
CPU read cycle, DMAC dual mode read cycle,
DMAC single mode read/write cycle
Corresponding Bits in Corresponding Bits in
WCR1 and WCR2 = 0 WCR1 and WCR2 = 1
CPU Write Cycle and
DMAC Dual Mode Write
Cycle (Cannot be
controlled by WCR1)*²
1, 3–5, 7
1 cycle fixed; WAIT signal 2 cycles fixed + wait state from WAIT signal
ignored
0, 2, 6 (long
1 cycle + long wait state, 1 cycle + long wait state*¹ + wait state from WAIT
wait available) WAIT signal ignored
signal
Notes: 1. The number of long wait states is set by WCR3.
2. When DRAME = 1, short pitch/long pitch is selected with the WW1 bit of the WCR1.
3. Pin wait cannot be used for the CS7 and WAIT pins of area 3 because they are
multiplexed.
For the CPU read cycle, DMAC dual mode read cycle and DMAC single mode read/write cycle,
the access cycle is completed in 1 state when the corresponding bits of WCR1 and WCR2 for
areas 1, 3–5, and 7 are cleared to 0 and the WAIT pin input signal is not sampled. When the bits
are set to 1, the WAIT signal is sampled and the number of states is 2 plus the number of wait
states in the WAIT signal. The WAIT signal is sampled at the rise of the system clock (CK)
directly preceding the second state of the bus cycle and the wait states are inserted as long as the
level is low. When a high level is detected, it shifts to the second state (final state). Figure 8.13
shows the wait state timing when accessing the external memory spaces of areas 1, 3, 4, 5, and 7.
130 RENESAS