SH7020 Datasheet, PDF (250/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

General registers are connected to the CPU by a 16-bit bus, so general registers can be written or
read by either word access or byte access. General registers are initialized to the output compare
register (no pin output) by a reset or in standby mode. The initial value is H'FFFF.
Table 10.5 General Registers A and B (GRA and GRB)
Channel Abbreviation
0
GRA0, GRB0
1
GRA1, GRB1
2
GRA2, GRB2
3
GRA3, GRB3
4
GRA4, GRB4
Function
Output compare/input capture dual register
Output compare/input capture dual register. Can also be set for
buffer operation in combination with the buffer registers (BRA, BRB)
Bit: 15
14
13
12
11
10
9
8
Bit name:
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Bit name:
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
10.2.8 Buffer Registers A and B (BRA, BRB)
Each buffer register is a 16-bit read/write register that is used in the buffer mode. The ITU has
four buffer registers, two each for channels 3 and 4 (table 10.6). Buffer operation can be set
independently by the timer function control register (TFCR) bits BFB4, BFA4, BFB3, and BFB3
bits. The buffer registers are paired with the general registers and their function changes
automatically to match the function of its corresponding general register.
The buffer registers are connected to the CPU by a 16-bit bus, so they can be written or read by
either word or byte access. Buffer registers are initialized to H'FFFF by a reset or in standby mode.
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