SH7020 Datasheet, PDF (220/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

T1 T2 T3 T4
T1 T2 T3 T4
CK
DREQ
Bus cycle _{CPU CPU CPU}
DMAC
CPU
DMAC
CPU
DACK
Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer
will be executed because the sampling is done at the second state of the DMAC cycle.
Figure 9.21 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level
detection and DACK active low) (Single address mode, bus cycle = Address/data multiplex
I/O bus cycle)
T1 T2 T3 T4
T1 T2 T3 T4
CK
DREQ
Bus cycle
CPU CPU CPU
DMAC(R)
DMAC
(W)
CPU
DMAC (R)
DMAC
(W)
CPU
DACK
DMAC (R): DMAC read cycle
DMAC (W): DMAC write cycle
Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA
transfer will be executed because the sampling is done at the second state of the
DMAC cycle.
Figure 9.22 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level
detection and DACK active low) (Dual address mode, bus cycle = Address/data multiplex
I/O bus cycle)
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