SH7020 Datasheet, PDF (491/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

CK
A21–A0
RAS
CAS
RD(Read)
T_p
T_r
T_c
T_c
T_c
T_c
t_AD
t_AD
Row address Column address Column address Column address
Column address
t_RASD1
t_RASD2
t_ASC t_CP
t_RDD
t_RSD
WRH, WRL,
WR(Read)
AD15–AD0
DPH, DPL
(Read)
DACK0
DACK1
(Read)
t_CAC1*^{1 tACP}
t_RAC1*^{3 tACC1*2 tRDS tRDH*4}
t_DACD1 t_DACD2
t_RDH*⁵
Notes: 1.
2.
3.
4.
5.
For t_CAC1, use t_cyc × 0.65 – 35 (for 35% duty) or t_cyc × 0.5 – 35 (for 50% duty) instead
of t_cyc – t_AD – t_ASC – t_RDS.
It is not necessary to meet the t_RDS specification as long as the t_CAC1 specification is
met.
For t_ACC1, use t_cyc – 44 instead of t_cyc – t_AD – t_RDS.
It is not necessary to meet the t_RDS specification as long as the t_ACC1 specification is
met.
For t_RAC1, use t_cyc × 1.5 – 35 instead of t_cyc × 1.5 – t_RASD1 – t_RDS.
It is not necessary to meet the t_RDS specification as long as the t_RAC1 specification is
met.
t_RDH is measured from A21—A0 or CAS, whichever is negated first.
t_RDH is measured from A21—A0, RAS, or CAS, whichever is negated first.
Figure 19.25 (a) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Read)
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