SH7020 Datasheet, PDF (101/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

3. When receiving the user break interrupt request, the interrupt controller checks its priority
level. The user break interrupt has priority level 15, so it is accepted only if the interrupt mask
level in bits I3–I0 in the status register (SR) is 14 or lower. When the I3–I0 bit level is 15, the
user break interrupt cannot be accepted but it is held pending until user break interrupt
exception processing is carried out. NMI exception processing sets I3–I0 to level 15, so a user
break cannot occur during the NMI service routine unless the NMI service routine itself begins
by reducing I3–I0 to level 14 or lower. Section 5, Interrupt Controller, described the handling
of priority levels in greater detail.
4. The INTC sends a request signal for a user break interrupt to the CPU. When the CPU receives
it, it starts user break interrupt exception processing. Section 5.4, Interrupt Operation, describes
interrupt exception processing in more detail.
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