SH7020 Datasheet, PDF (216/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Figure 9.13 to 9.22 show the sampling timing of the pin DREQ in the cycle steal mode for
each bus cycle. When no DREQ input is detected at the sampling after the aforementioned
DREQ detection, the next sampling occurs in the next stage in which a DACK signal is output.
If no DREQ input is detected at this time, sampling occurs at every state thereafter.
CK
DREQ
Bus cycle
CPU CPU CPU DMAC CPU CPU CPU CPU
DACK
Figure 9.13 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level
detection and DACK active low) (Single address mode, bus cycle = 1 state)
CK
DREQ
Bus cycle
CPU CPU CPU DMAC (R) DMAC (W) CPU CPU CPU
DACK
DMAC (R): DMAC read cycle
DMAC (W): DMAC write cycle
Note: Illustrates the case when DACK is output during the DMAC Read cycle.
Figure 9.14 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level
detection and DACK active low) (Dual address mode, bus cycle = 1 state)
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