SH7020 Datasheet, PDF (238/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

10.1.4 Register Configuration
Table 10.3 summarizes the ITU register configuration.
Table 10.3 Register Configuration
Channel Name
Abbrevi-
ation
R/W
Initial
Value
Access
Address*¹ Size
Shared Timer start register
TSTR R/W H'E0/H'60 H'5FFFF00 8
Timer synchro register
TSNC R/W H'E0/H'60 H'5FFFF01 8
Timer mode register
TMDR R/W H'80/H'00 H'5FFFF02 8
Timer function control register TFCR R/W H'C0/H'40 H'5FFFF03 8
Timer output control register TOCR R/W H'FF/H'7F H'5FFFF31 8
0
Timer control register 0
TCR0 R/W H'80/H'00 H'5FFFF04 8
Timer I/O control register 0 TIOR0 R/W H'88/H'08 H'5FFFF05 8
Timer interrupt enable
register 0
TIER0 R/W H'F8/H'78 H'5FFFF06 8
Timer status register 0
TSR0 R/(W)*² H'F8/H'78 H'5FFFF07 8
Timer counter 0
TCNT0 R/W H'00
H'5FFFF08 8, 16, 32
H'5FFFF09 8, 16, 32
General register A0
GRA0 R/W H'FF
H'5FFFF0A 8, 16, 32
H'5FFFF0B 8, 16, 32
General register B0
GRB0 R/W H'FF
H'5FFFF0C 8, 16
H'5FFFF0D 8, 16
1
Timer control register 1
TCR1 R/W H'80/H'00 H'5FFFF0E 8
Timer I/O control register 1 TIOR1 R/W H'88/H'08 H'5FFFF0F 8
Timer interrupt enable
register 1
TIER1 R/W H'F8/H'78 H'5FFFF10 8
Timer status register 1
TSR1 R/(W)*² H'F8/H'78 H'5FFFF11 8
Timer counter 1
TCNT1 R/W H'00
H'5FFFF12 8, 16
H'5FFFF13 8, 16
General register A1
GRA1 R/W H'FF
H'5FFFF14 8, 16, 32
H'5FFFF15 8, 16, 32
General register B1
GRB1 R/W H'FF
H'5FFFF16 8, 16, 32
H'5FFFF17 8, 16, 32
222 RENESAS