SH7020 Datasheet, PDF (173/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

CK
A21–
A0
External
CSn
space
write
WR
AD15–
AD0
Internal address
On-chip
peri-
pheral
module
write
Internal
write
strobe
Internal
data bus
On-chip
peri-
pheral
module
read
Internal
read
strobe
Internal
data bus
External space writing
On-chip peripheral module read/write
T1
T2
T3
T4
T5
External space address
External space
address
Write data
On-chip peripheral module address
Write data
Read data
Figure 8.34 Warp Mode Timing (Access to On-Chip Peripheral Module and External Write
Cycle)
8.9 Wait State Control
The WCR1–WCR3 registers of the BSC can be set to control sampling of the WAIT signal when
accessing various areas and the number of bus cycle states. Table 8.11 shows the number of bus
cycle states when accessing various areas.
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