SH7020 Datasheet, PDF (38/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

31
9
0 ^{Multiply and accumulate (MAC) registers}
(sign extended)
MACH
high and low (MACH, MACL): Store the
results of multiply and accumulate opera-
MACL
tions. MACH is sign-extended when read
because only the lowest 10 bits are valid.
31
PR
0
Procedure register (PR): Stores a return
address from a subroutine procedure.
31
PC
0 _{Program counter (PC): Indicates the}
fourth byte (second instruction) after
the current instruction.
Figure 2.3 System Registers
2.1.4 Initial Values of Registers
Table 2.1 lists the values of the registers after reset.
Table 2.1 Initial Values of Registers
Classification
General register
Control register
Register
R0–R14
R15 (SP)
SR
System register
GBR
VBR
MACH, MACL, PR
PC
Initial Value
Undefined
Value of the stack pointer in the vector address table
Bits I0-I3 are 1111(H'F), reserved bits are 0, and other
bits are undefined
Undefined
H'00000000
Undefined
Value of the program counter in the vector address
table
2.2 Data Formats
2.2.1 Data Format in Registers
Register operands are always long words (32 bits). When the memory operand is only a byte (8
bits) or a word (16 bits), it is sign-extended into a long word when stored into a register (figure
2.4).
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