SH7020 Datasheet, PDF (7/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Organization of This Manual
Table 1 describes how this manual is organized. Figure 1 shows the relationships between the
Sections within this manual.
Table 1 Manual Organization
Category
Overview
Section Title
1. Overview
CPU
2. CPU
Operating
Modes
Internal
Modules
Clock
Buses
Timers
3. Operating
Modes
4. Exception
Processing
5. Interrupt
Controller
6. User Break
Controller
7. Clock Pulse
Generator
8. Bus State
Controller
9. Direct Memory
Access
Controller
10. 16-Bit
Integrated-
Timer Pulse
Unit
Data
Processing
11. Programmable
Timing Pattern
Controller
12. Watchdog
Timer
13. Serial
Communica-
tion Interface
Abbrevi-
ation
—
CPU
—
—
INTC
UBC
CPG
BSC
DMAC
ITU
TPC
WDT
SCI
Contents
Features, internal block diagram, pin layout,
pin functions
Register configuration, data structure.
instruction features, instruction types,
instruction lists
MCU mode, PROM mode
Resets, address errors, interrupts, trap
instructions, illegal instructions
NMI interrupts, user break interrupts, IRQ
interrupts, on-chip module interrupts
Break address and break bus cycles selection
Crystal pulse generator, duty correction circuit
Division of memory space, DRAM interface,
refresh, wait state control, parity control
Auto request, external request, on-chip
peripheral module request, cycle steal mode,
burst mode
Waveform output mode, input capture
function, counter clear function, buffer
operation, PWM mode, complementary PWM
mode, reset synchronized mode, synchronized
operation, phase counting mode, compare
match output mode
Compare match output triggers, non-overlap
operation
Watchdog timer mode, interval timer mode
Asynchronous mode, clock synchronous
mode, multiprocessor communication function