SH7020 Datasheet, PDF (445/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

18.1.2 Register
Table 18.2 summarizes the register related to the power-down state.
Table 18.2 Standby Control Register (SBYCR)
Name
Standby control register
Abbreviation R/W Initial Value Address Access size
SBYCR
R/W H'1F
H'5FFFFBC 8, 16, 32
18.2 Standby Control Register (SBYCR)
The standby control register (SBYCR) is an 8-bit register that can be read or written to. It is set in
order to enter the standby mode and also sets the port states in standby mode. The SBYCR is
initialized to H'1F when reset.
Bit: 7
6
5
4
3
2
1
0
Bit name: SBY
HIZ
—
—
—
—
—
—
Initial value: 0
0
0
1
1
1
1
1
R/W: R/W R/W
—
—
—
—
—
—
• Bit 7 (standby (SBY)): SBY enables transition to the standby mode. The SBY bit cannot be set
to 1 while the timer enable bit (bit TME) in timer control/status register TCSR of watchdog
timer WDT is set to 1. To enter the standby mode, clear the TME bit to 0 to halt the WDT and
set the SBY bit.
SBY
0
1
Description
Executing SLEEP instruction puts the LSI into sleep mode (initial value)
Executing SLEEP instruction puts the LSI into standby mode
• Bit 6 (port high-impedance (HIZ)): HIZ selects whether I/O ports remain in their previous
states during standby, or are placed in the high-impedance state when the standby mode is
entered. The HIZ bit cannot be set to 1 while the TME bit is set to 1. To place the pins of the
I/O ports in high impedance, clear the TME bit to 0 before setting the HIZ bit.
HIZ
Description
0
Port states are maintained during standby (initial value)
1
Ports are placed in the high-impedance state in standby
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