SH7020 Datasheet, PDF (301/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

10.6 Notes and Precautions
This section describes contention and other matters requiring special attention during ITU
operations.
10.6.1 Contention between TCNT Write and Clear
If a counter clear signal occurs in the T3 state of a TCNT write cycle, clearing the counter takes
priority and the write is not performed. The timing is shown in figure 10.58.
TCNT write cycle by CPU
T1
T2
T3
CK
Address
Internal write signal
TCNT address
Counter clear signal
TCNT
N
H' 0000
Figure 10.58 Contention between TCNT Write and Clear
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